An FSM can assign a state to any convenient bit pattern. The choice affects how many flip-flops store the state and how complex the next-state and output logic becomes. Binary encoding uses the fewest state bits; one-hot encoding gives each state its own bit. Neither is always better. The right choice depends on the number of states, target technology, timing, reset and recovery requirements, and how outputs decode.
This article compares both encodings for the same four-state cycle. We derive the equations, count registers, examine the effect of state bits on logic depth, and discuss invalid patterns. The example shows why one-hot logic can be simple without proving that it is faster, and why the lower register count of binary encoding does not guarantee a smaller or quicker complete implementation.
What state encoding represents
A state name such as IDLE or SEND describes an abstract condition of the machine. Hardware stores that condition as bits. If an FSM has N states, binary encoding needs at least ⌈log₂N⌉ bits to give each state a unique code. One-hot encoding uses N bits and assigns exactly one bit high for each legal state. Other encodings—Gray, output-oriented, or custom—are also possible.
State assignment changes the truth tables for next-state bits and outputs. After choosing codes, build the state table, then minimize each next-state and output function. A K-map does not choose the abstract behavior; it simplifies the equations for the encoding you selected. It is common for one encoding to make state transition logic simple while another makes output decoding simple.
The comparison must include more than gate count. A design may trade registers for combinational logic, clock load for decode depth, or nominal area for easier timing closure. Synthesis tools can restructure logic and choose library-specific cells, so hand-derived equations are a guide to structure rather than an exact prediction of mapped area or frequency.
Binary encoding of a four-state cycle
Consider four states S0→S1→S2→S3→S0 with no external input. Assign S0=00, S1=01, S2=10, and S3=11, using state bits A,B. Two flip-flops are sufficient. The transition table is:
| Present state | AB | Next state | A⁺B⁺ |
|---|---|---|---|
| S0 | 00 | S1 | 01 |
| S1 | 01 | S2 | 10 |
| S2 | 10 | S3 | 11 |
| S3 | 11 | S0 | 00 |
For D flip-flops, the next-state bit functions are A⁺=A⊕B and B⁺=B′. This follows by placing the next A and B values into separate two-variable K-maps. A⁺ is high at 01 and 10, while B⁺ is high at 00 and 10. The cycle uses two registers and modest combinational logic. If an output is high only in S3, it is AB, requiring a two-input decode.
One-hot encoding of the same cycle
Now use four state bits Q0,Q1,Q2,Q3, with exactly one bit high. Let Q0 represent S0, Q1 represent S1, and so on. Each transition shifts the active bit to the next position. With D flip-flops, the equations are D0=Q3, D1=Q0, D2=Q1, and D3=Q2. Each next-state input is just a wire from the previous state's register output.
A state output can also be direct: if Z is high in S3, then Z=Q3. A transition that depends on an external input may add simple qualification to one of these wires. For example, a state that stays active while enable E=0 and advances when E=1 may have a next-state expression combining the current-state bit and the predecessor term. One-hot structure can make the state condition explicit, though a busy transition graph can still need substantial logic.
The one-hot code has four legal patterns: 0001, 0010, 0100, and 1000, depending on bit-order convention. The all-zero pattern and patterns with multiple ones are invalid. Reset logic must establish the chosen initial bit. If recovery from invalid states is required, the table must define whether the machine returns to S0, asserts an error, or enters a safe state.
Compare resources and logic
| Consideration | Binary | One-hot |
|---|---|---|
| State flip-flops for 4 states | 2 | 4 |
| State decode | May require a bit combination | Often one state bit |
| Next-state logic in the cycle example | XOR and inversion | Register-to-register shift |
| Legal encodings | All 2-bit patterns are used | Only one-hot patterns are legal |
| Clock and reset load | Fewer state elements | More state elements to clock/reset |
For the four-state ring, one-hot next-state logic looks especially simple, but it uses twice as many flip-flops. For a larger machine, a binary code uses roughly logarithmic register count, while one-hot uses one register per state. If flip-flops are area-intensive or clock power is important, binary may be attractive. If timing through state decoding is critical, one-hot may reduce logic depth in some designs.
Those are tendencies, not guarantees. An FPGA may have abundant flip-flops and dedicated routing, making one-hot competitive. An ASIC library may offer compact complex gates that favor a binary implementation. The synthesis tool can optimize either encoding, and a state assignment with outputs embedded in the code may beat both textbook defaults.
Output decoding
In binary encoding, a Moore output that is high in one state is usually a Boolean decode of the state bits. For the four-state example, S3=11 yields Z=AB. If many outputs correspond to individual states, the machine may need several decoders. A one-hot implementation can often use Z=Q3 directly. If outputs are shared across groups of states, binary expressions may instead simplify into broad implicants, while one-hot may require ORing multiple state bits.
Mealy outputs depend on state and inputs, so both encodings require some combinational logic. One-hot can make the state portion of the condition a single signal, but the input qualification still remains. If outputs are timing-critical, compare the whole path from state register and external input through the output logic, not only the next-state equations.
Output encoding and state encoding can be co-designed. Sometimes a state bit can directly represent a control signal, but that can alter transition complexity or create invalid states. Any such choice must preserve the state diagram, output timing, and reset behavior. A K-map can help compare the resulting equations after each candidate assignment is written down.
Invalid states and reset
For binary encoding with exactly four states and two bits, all four patterns are assigned, so there are no unused codes. For one-hot encoding, most bit patterns are invalid. If one-hot state bits become all zero or multiple bits high, the nominal transition equations may not recover unless recovery behavior is designed. A watchdog, parity check, explicit valid-state detector, or self-correcting transition logic may be appropriate depending on the fault model.
Reset must set exactly the chosen initial encoding: 00 for binary S0 or the one-hot bit for S0. Asynchronous reset release and clock timing can cause implementation concerns beyond Boolean minimization. If reset is synchronous, include it as an input condition in the next-state functions; if it is asynchronous, use the flip-flop's reset pin and obey its timing requirements.
Do not automatically treat unused patterns as don't-cares. If invalid-state recovery is required, specify the next state and outputs for those patterns. See the guide to unused FSM state codes for a detailed discussion of reachability assumptions and safe minimization.
Target technology matters
The equations from a K-map are technology-independent Boolean forms. A mapped circuit is not. The target may have dedicated LUTs, abundant flip-flops, integrated enables, fast carry chains, complex gates, or specialized reset cells. Those features affect the cost of an encoding. An FPGA synthesis tool may automatically recode an FSM to improve speed or area, while an ASIC flow may preserve a user-specified encoding to meet safety or verification requirements.
Measure the synthesized result when the implementation choice matters. Compare register count, combinational cell count, logic depth, critical path, clock power, reset routing, and constraints on invalid states. Also check whether synthesis changed the encoding; the netlist may no longer match the handwritten state bits. Equations are useful for reasoning, but mapped timing and resource reports are the evidence for a specific device.
A practical selection process
- Count states and define requirements. Include reset, illegal-state recovery, outputs, and timing goals.
- Choose candidate encodings. Compare binary, one-hot, and any output-oriented or Gray assignment that fits the behavior.
- Build each state table. Derive next-state and output functions independently.
- Minimize or synthesize. Use K-maps for small functions and a synthesis flow for larger machines.
- Compare implementation results. Check timing, area, register use, power, and reset behavior.
- Verify recoding and recovery. Confirm the implementation preserves the abstract transitions and required fault response.
For four states, binary encoding uses two flip-flops and one-hot uses four. In the ring example, binary equations are A⁺=A⊕B and B⁺=B′; one-hot equations simply rotate the active bit. That comparison is concrete, but it does not settle every design. State encoding is a tradeoff between storage, decode, transition logic, and the capabilities of the target technology.
Compare the cycle as a timing question
To compare timing fairly, follow a path from a register output through the next-state logic back to a register input. In the binary version, A⁺ includes an XOR of A and B, while B⁺ is an inversion. In the one-hot ring, each next-state input can be driven by a neighboring state bit. That suggests a shallower path for the one-hot version, but the physical delay also includes clock-to-Q, routing, setup time, and any enable or reset logic.
Then compare the output path. Binary Z=AB requires a decode gate; one-hot Z=Q3 can be a direct state bit. If the output is high in many states, the one-hot form may instead require an OR of several bits. A design with a critical output path may favor a different encoding from a design whose register-to-register path is critical. Timing reports reveal which path actually limits the clock period.