An ALU (arithmetic logic unit) — the part of a processor that actually does addition, subtraction, comparisons, and bitwise operations — sounds like it should need some fundamentally different kind of logic than the small examples covered throughout this site. It doesn't. An ALU is a combination of exactly the same combinational building blocks, wired together and selected between, not a separate category of circuit.
The adder core
Every ALU's arithmetic path is built from chained full adders — the same circuit covered in full in Half Adder vs. Full Adder and the full adder example, repeated once per bit of the ALU's width, each stage's carry-out feeding the next stage's carry-in. A 32-bit ALU's adder is, structurally, the exact same 3-input Sum/Carry-out logic, just repeated 32 times with the carries chained together.
Selecting between operations
An ALU doesn't just add — it also subtracts, and typically supports bitwise AND, OR, and XOR as separate selectable operations. Choosing which result to output based on a function-select code is exactly a multiplexer's job, the same selection logic covered in Designing a 4-to-1 Multiplexer — just with more inputs (one per supported operation) and a wider select code.
Subtraction specifically is usually done without a separate subtractor circuit at all: A − B is computed as A + (two's complement of B), which just means feeding B through inverters and setting the adder's initial carry-in to 1 — reusing the same adder hardware rather than duplicating it.
Comparisons and status flags
Zero, negative, overflow, and carry flags — and any direct greater-than/less-than/equal outputs — are built from the same comparison logic in the magnitude comparator example, scaled up to the ALU's full bit width. The "equals" comparison in particular still traces back to the same XNOR-based, structurally unsimplifiable pattern covered there.
Where K-maps actually fit into ALU design
Nobody minimizes an entire 32-bit ALU as one giant K-map — that's exactly the "past 6 variables" territory covered in How Many Variables Can a Karnaugh Map Handle?. What actually gets K-map-minimized is each small sub-block individually: a single full-adder stage, a single bit of the function-select logic, a single comparator bit — each one small enough to fit comfortably in 2-6 variables, then replicated and wired together at scale. The K-map's job is optimizing the repeated unit, not the whole assembled machine.
See the actual sub-blocks an ALU is built from: full adder, magnitude comparator, and the multiplexer selection logic that ties them together.