NAND and NOR are each "universal" gates — either one alone can implement any Boolean function, with no AND, OR, or NOT gates needed at all. That matters in practice because NAND and NOR are typically the cheapest, fastest gates to fabricate at the transistor level, so a lot of real digital hardware is built almost entirely from one or the other. Converting a minimal SOP or POS expression into an all-NAND or all-NOR circuit is a mechanical process once you know the trick — double negation plus De Morgan's theorem, applied once.
Why NAND alone can build an SOP circuit
A NAND gate is just an AND gate with its output inverted: NAND(A,B) = (A·B)′. Take any SOP expression and add a double negation around the whole thing — which changes nothing, since negating twice is the identity — and then apply De Morgan's theorem to push one of those negations inward, and every AND and OR in the expression turns into a NAND.
Take F = AB + CD. Double-negating gives F = (AB + CD)′′, and pushing the outer negation inward via De Morgan turns the OR into an AND of negated terms: F = ((AB)′ · (CD)′)′. Every operation left in that expression is exactly a NAND: (AB)′ is NAND(A,B), (CD)′ is NAND(C,D), and the outermost negation-of-an-AND is a NAND of those two results:
This holds for any number of SOP terms, not just two — the majority function from the truth-table walkthrough, F = BC + AC + AB, converts the same way into a NAND of three NAND outputs, one per term, with no AND or OR gates anywhere in the final circuit.
Why NOR alone can build a POS circuit
The same trick runs in reverse for POS expressions using NOR, since NOR(A,B) = (A+B)′. Take F = (A+B)(C+D), double-negate, and push the outer negation inward: F = ((A+B)′ + (C+D)′)′ — every operation is now a NOR. (A+B)′ is NOR(A,B), (C+D)′ is NOR(C,D), and the outer step is a NOR of those two:
The pattern to remember
SOP converts to NAND-of-NANDs; POS converts to NOR-of-NORs. In both cases the structure is identical to the original AND-OR or OR-AND circuit — same number of gates, same number of levels — just every gate becomes the same universal type, with no separate inverters needed anywhere, since the inversion is built into NAND and NOR already.