Moore and Mealy machines differ in what their outputs depend on. A Moore output depends only on the present state. A Mealy output depends on present state and current inputs. The distinction changes the state table and the Boolean functions minimized with K-maps, and it can change when an output responds within a clock cycle.
This guide designs a sampled rising-edge detector both ways. The Mealy version uses one state bit to remember the previous input sample and derives its output from that state and the current input. The Moore version adds a pulse state so the output is encoded in the state itself. We derive the next-state and output equations, walk through an input sequence, and discuss latency, glitches, and state encoding.
Moore and Mealy definitions
For a Moore machine, output Z is a function of current state: Z=g(S). For a Mealy machine, output Z is a function of current state and input: Z=g(S,X). Both models have next state S⁺=f(S,X). The next-state function always depends on current state and usually on inputs; it is the output function that distinguishes the two models.
A Moore output often changes only when the state register changes at a clock edge, which can simplify interface timing. A Mealy output can respond to an input change without waiting for a state update, which may reduce state count or latency. That responsiveness can also create glitches if input and state paths have different delays. These are design tendencies; actual behavior depends on whether inputs are synchronous, how outputs are registered, and what the receiving circuit expects.
A K-map can minimize each next-state bit and each output bit. For a Moore output, its map axes are state bits. For a Mealy output, include the external input bits too. Keep present-state bits distinct from next-state bits in the table; each map represents a combinational function of current signals.
Mealy rising-edge detector
Assume a synchronous input X is sampled once per clock. Let state Q store the previous sampled value. The machine should produce a pulse when the previous sample was 0 and the current sample is 1. For a Mealy machine, the next state is Q⁺=X and the output is Z=Q′X. When Q=0 and X=1, a rising edge is detected; in all other state/input combinations, Z=0.
| Present Q | Current X | Next Q⁺ | Mealy Z | Meaning |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | Input remains low |
| 0 | 1 | 1 | 1 | Rising edge detected |
| 1 | 0 | 0 | 0 | Input falls |
| 1 | 1 | 1 | 0 | Input remains high |
The state register holds only the previous input sample. If X is a raw asynchronous signal, it must be synchronized before this FSM to avoid metastability; the edge detector itself does not perform synchronization. If X is already synchronous to the clock, the table models its sampled behavior.
K-map equations for Mealy logic
There are two variables in the next-state function: current Q and X. Since Q⁺ equals X in every row, its K-map reduces immediately to Q⁺=X. The output map has a single 1 at Q=0,X=1; therefore Z=Q′X. This is already a minimal product term. The equations for a D flip-flop are D=X and Z=Q′X.
Trace a sample. Suppose the previous state is Q=0 and the input X becomes 1 before the active clock edge. The Mealy output becomes 1 through combinational logic while Q is still 0. At the clock edge, the register captures Q⁺=1; after that, Z=Q′X becomes 0. The pulse is associated with the interval in which the old state and current input indicate a rising edge. If the receiving logic samples only at a clock edge, the exact observation depends on input setup and edge timing.
This behavior is one reason Mealy outputs can be described as more immediate: output logic sees the current input. It is also why the pulse width and hazard behavior need attention. A brief input glitch while Q=0 can create a brief output glitch. A synchronous input assumption should be stated, and a pulse that must be captured reliably may need to be registered or stretched.
Moore version with a pulse state
A Moore output cannot depend directly on X, so encode a state in which the output pulse is high. Use three states: S0 means the previous sample was low; S1 means the previous sample was high; P means a rising edge has been detected and the Moore output is asserted. Transitions are: S0 with X=0 stays S0; S0 with X=1 goes to P; S1 with X=0 goes to S0; S1 with X=1 stays S1; P with X=0 goes to S0; P with X=1 goes to S1. Output Z=1 only in P.
Encode S0=00, S1=01, P=10 using bits A,B. Treat 11 as an unused code with next state 00 and output 0. The table yields A⁺=A′B′X, B⁺=X(A′B+AB′)=X(A⊕B), and Z=AB′. Check each legal state: from S0=00, X=0 gives 00 and X=1 gives 10; from S1=01, X=0 gives 00 and X=1 gives 01; from P=10, X=0 gives 00 and X=1 gives 01. The output decode is high in 10 only.
These equations can be derived with three-variable maps over A,B,X. The don't-care choices for state 11 should be treated according to the recovery requirement. We specified recovery to S0, which makes the equations above valid for 11 as well: A′B′X is zero and X(A′B+AB′) is zero when A=B=1. If recovery or output safety differs, update the table and maps.
Compare timing and state count
| Property | Mealy detector | Moore detector |
|---|---|---|
| State storage | One bit, previous sample | Three encoded states |
| Output equation | Z=Q′X | Z=AB′ |
| Output depends on current X | Yes | No |
| Input response | Can respond between clock edges | Changes with state at a clock edge |
| Pulse timing | Depends on input and old state timing | Pulse occupies the P state interval |
The Mealy version uses fewer registers and produces its indication from the current input and remembered previous value. The Moore version adds a state to represent the pulse, which can make the output independent of combinational input changes. Depending on the sampling convention, the Moore pulse may be observed in the cycle following the input sample that caused the transition. The interface specification should define when the event must be visible.
It is possible to register a Mealy output or restructure a Moore machine to alter latency. Those changes affect the required behavior, so compare waveforms at the interface rather than relying on the state-model labels alone. Neither model automatically guarantees glitch-free outputs if the output passes through combinational decoding; registered outputs are a common choice for stable synchronous interfaces.
Verify a sample sequence
Let the sampled input sequence be 0,0,1,1,0,1. In the Mealy design, initialize Q=0. The first two zeros produce no pulse; the first 1 produces Z=1 because the old Q is 0; the second 1 produces no pulse because Q is now 1; the 0 produces no pulse and updates Q to 0; the final 1 produces another pulse. The output sequence at each sample is 0,0,1,0,0,1, assuming the value is evaluated using the pre-edge state and current sample.
For the Moore design, the transition from S0 on X=1 enters P, so Z is high while the machine is in P after the state transition. On the next clock, it leaves P based on the new input. This represents a state-registered pulse and can be viewed as shifted relative to the combinational Mealy indication. A timing diagram should state whether outputs are labeled before or after each active edge to avoid off-by-one confusion.
Test input sequences with repeated highs, repeated lows, and alternating values. Also test reset: if reset sets the previous-sample state to 0, an initially high input may be interpreted as a rising event on the first evaluation. If that is undesirable, reset or initialization policy must specify how the first sample is treated.
Choosing the output model
Choose a Mealy output when the specification requires an immediate response to current input and the receiving logic can tolerate or filter the combinational path. Choose a Moore output when a state-based registered indication is preferable and an extra state or cycle is acceptable. Interface timing, pulse width, and glitch sensitivity are more important than a blanket rule that one model is simpler.
A Mealy implementation can have fewer states, but its outputs can change between clock edges. A Moore implementation can offer state-aligned outputs, but decoding a state may still glitch if multiple bits change at different times. A registered output or one-hot state assignment can address particular timing issues, but should be chosen based on the actual circuit and verified after synthesis.
State encoding also changes the output K-map. A Moore output may be a single state bit under one-hot encoding and a multi-literal decode under binary encoding. A Mealy output includes input variables and may simplify or factor with next-state logic. See binary versus one-hot state encoding for how the encoding affects equations and registers.
A practical workflow
- Write the timing contract. Define when inputs are sampled and when outputs must respond.
- Draw the state diagram. Include every transition condition and output behavior.
- Write the full table. Separate present state, input, next state, and output columns.
- Choose Moore or Mealy semantics. Make output dependencies explicit.
- Build maps per function. Include state bits and external inputs as required.
- Check reset and unused states. Define initialization and recovery.
- Verify with a timing trace. Use input sequences that exercise boundary transitions.
- Review implementation timing. Synchronous assumptions and output registration affect real behavior.
The edge detector shows the central difference in equations: Mealy Z=Q′X, while the Moore version asserts Z based on the pulse state. Both can implement useful event detection, but they expose the event at different points in the clocked behavior. A complete state table and timing interpretation make the K-map derivation precise.