A Boolean expression describes the correct output for stable input combinations. A physical circuit also has propagation delay, so its output can briefly behave differently while inputs move between combinations. These temporary pulses are called hazards. The three common categories are static-1, static-0, and dynamic hazards. They describe different intended transitions, and they call for different checks.
Karnaugh maps are useful for finding static hazards in two-level SOP and POS implementations. They reveal whether adjacent cells with the same required output share an implicant. Dynamic hazards are more complex: an output that should change once can change several times, usually because signals travel through reconvergent paths and multiple logic levels. This guide separates the concepts, works a static example, explains the limits of consensus-term fixes, and gives a practical verification workflow.
Three hazard definitions
A static-1 hazard occurs when the ideal output is 1 both before and after a single input changes, but the circuit may pulse low during the transition. A static-0 hazard is the dual case: the ideal output is 0 at both endpoints, but a pulse high may appear. A dynamic hazard occurs when the ideal output should change once, from 0 to 1 or 1 to 0, but the real circuit changes multiple times before settling.
“Static” refers to the output value that should remain unchanged; it does not mean the inputs are static. One input is changing while the output should stay constant. “Dynamic” refers to the intended output transition itself. A glitch on a waveform is not automatically a hazard in every engineering sense: its significance depends on whether downstream logic can observe it, whether it violates timing or pulse-width constraints, and what input transitions the interface permits.
Hazard analysis typically assumes that only one input changes at a time and that gate delays are positive but not identical. Real systems can have simultaneous changes, analog effects, metastability, clock skew, and pulse filtering. Those issues require additional timing and interface analysis. The taxonomy is a useful starting point, not a substitute for the implementation's timing model.
Static-1 in SOP logic
In a two-level sum-of-products circuit, the output is an OR of product terms. If two adjacent input assignments both require output 1, they are safe from a static-1 hazard when at least one product term covers both assignments. That common term can remain high while the changing input propagates through other paths. On a K-map, this means every relevant adjacent pair of 1-cells should lie inside a shared group.
For example, consider F(A,B,C)=A′B+AC with B=1 and C=1 while A changes. At A=0, A′B is 1; at A=1, AC is 1. The output should remain 1, but the two product paths can switch at different times, briefly making both products 0. The K-map cells for the two endpoint assignments are adjacent in A, yet the two displayed terms cover them separately. Add the consensus term BC: Fhf=A′B+AC+BC. When B=C=1, BC stays high regardless of A, bridging the transition.
The added term does not change the stable truth table. If BC=1, then either A=0 makes A′B=1 or A=1 makes AC=1, so BC never adds a new on-set assignment. It only overlaps an already-covered region. The article on K-map static hazards and consensus terms explores this example with group selection and algebra.
Static-0 in POS logic
A POS network is an AND of sum terms. To keep its output at 0 across a one-input transition, at least one sum factor should stay at 0 at both endpoint assignments. Therefore, in a two-level POS design, every adjacent pair of required zero cells should share a zero-group. A zero-group becomes a sum factor, and a missing shared factor indicates a possible static-0 hazard.
For F(A,B,C)=(A+B)(A′+C), zeros occur at minterms 0,1,4,6. The zero pairs {0,1} and {4,6} produce the two factors. But cells 0=000 and 4=100 are also adjacent because only A changes; no single factor covers both. If A changes while B=C=0, the first factor may rise before the second factor falls, allowing a brief high output. Add the redundant factor B+C, which is zero on both 000 and 100. The resulting POS expression is hazard-aware for that transition under the standard model. See the complete static-0 POS walkthrough.
The SOP and POS checks are duals. For SOP, group required 1s and inspect adjacent 1-pairs for a common product term. For POS, group required 0s and inspect adjacent zero-pairs for a common sum factor. Do not apply the SOP literal-reading rule to POS: when a zero group is translated, a bit fixed at 0 gives an uncomplemented literal in the sum, while a bit fixed at 1 gives a complemented literal.
What makes a hazard dynamic
A dynamic hazard means the output is supposed to make one transition, such as 0→1, but the circuit output may bounce: 0→1→0→1 before settling. This is different from a static hazard, where the output should not transition at all. Dynamic behavior is associated with multilevel logic and reconvergent paths, where a signal or its complement travels through paths with different numbers of gates and different delays. Several internal events can reach an output in a sequence that produces multiple crossings.
It is unsafe to diagnose every multi-pulse waveform by looking only at a simplified equation. The circuit topology, gate delays, input arrival times, fanout, and inertial or transport delay model all influence the waveform. A two-level network with a single-input transition has simpler hazard properties than an arbitrary factored network, which is why static hazards have direct K-map criteria. Dynamic hazards generally need path-delay analysis or gate-level simulation on the actual implementation.
As a conceptual timing trace, imagine a function whose final output should rise after an input changes. One internal path rises quickly and drives the output high; a second, longer path later changes a controlling signal and drives the output low; a third path eventually restores the correct high value. The truth table says only that the initial and final values are 0 and 1. It does not describe the intermediate sequence. This is why checking endpoint equivalence cannot prove glitch-free timing.
What consensus terms fix
The consensus theorem gives a systematic redundant term for certain two-level SOP structures: AB+A′C+BC = AB+A′C. The term BC is redundant for stable logic and bridges the transition where B=C=1 and A changes. The POS dual adds a sum factor to cover adjacent zero assignments. These are targeted fixes for static hazards in specified single-input transitions.
A consensus term is not a universal cure for dynamic hazards. Adding one term can remove a static gap in a two-level cover, but it does not automatically equalize path delays, eliminate reconvergence, constrain multiple inputs, or ensure that a multi-level network transitions only once. If the implementation is factored, synthesized, or mapped to complex cells, recheck hazard behavior after those transformations. The synthesis tool may remove redundant logic unless preservation constraints or timing requirements tell it otherwise.
It is also important to separate a logically redundant term from a physically unnecessary term. Under ordinary Boolean equivalence, adding BC in the example changes nothing. For an asynchronous control signal, the same added overlap may prevent a pulse that could trigger downstream state. In that setting the term has implementation value even though it does not change the truth table. The specification should state whether hazard freedom is required.
Timing and simulation
A zero-delay simulator evaluates combinational logic as if all gates settle instantly. It can prove Boolean equivalence but cannot show propagation hazards. A gate-level simulation with realistic delays can reveal pulses for tested transitions. However, simulation is only as good as its delay model and test coverage; it does not prove behavior for every delay corner or input arrival order.
Use static timing analysis to understand path delays, but recognize that standard setup/hold analysis may not report every combinational glitch as a functional hazard. For asynchronous interfaces, pulse-sensitive controls, or clock enables, analyze the relevant transitions explicitly. Consider whether a downstream element samples the signal during the pulse, whether a minimum pulse width is required, and whether the signal should be synchronized or registered.
When a combinational output drives a clock, asynchronous reset, set, latch enable, or external interrupt, a short glitch can have disproportionate consequences. Often the right architectural fix is to register the output or redesign the handshake rather than accumulating hazard terms. A K-map can help derive the combinational logic, but it cannot decide whether a combinational path is an appropriate interface.
A practical checking workflow
- Define the transition model. State whether one input changes at a time and which input combinations are reachable.
- Minimize for stable logic. Derive SOP, POS, or factored candidates from the truth table.
- Check static transitions. In SOP inspect adjacent 1s; in POS inspect adjacent 0s. Look for a common implicant or factor.
- Add consensus coverage where required. Document that the added term is redundant for Boolean value and identify the transition it protects.
- Inspect the implemented topology. Synthesis and technology mapping can alter the path structure.
- Use timing-aware evidence. Simulate or analyze the actual gates for relevant input arrival orders and delay corners.
- Protect sensitive interfaces. Register or otherwise condition signals whose pulses could cause unsafe behavior.
Keep a transition table alongside the truth table. For each pair of adjacent assignments that matters, record which variable changes, the required output at both endpoints, and the term that protects the transition. This makes assumptions visible and helps reviewers distinguish an omitted K-map group from a timing issue outside the Boolean model.
Where K-Maps stop
Karnaugh maps represent stable Boolean function values. Their geometry captures single-bit adjacency, which is why they are effective for static hazard checks. They do not encode propagation delay, analog slew, inertial filtering, metastability, or simultaneous input switching. A correct K-map expression is necessary for logic correctness but not sufficient for a timing guarantee.
For simple two-level combinational circuits, the map can show exactly where a shared implicant is missing. For larger or multilevel networks, inspect the netlist and use timing-aware methods. If the system contract does not require glitch-free behavior, a transient may be harmless; if it does, say so explicitly and verify the implementation against that requirement. Static-1, static-0, and dynamic hazards are easier to manage when the stable logic, transition model, and physical timing are treated as related but distinct questions.
A useful summary is: a static hazard is an unwanted pulse while the output should stay the same; a dynamic hazard is extra transitions while the output should change once. K-maps and consensus terms help with the two-level static cases. Dynamic hazards and implementation-level behavior require topology and timing analysis.